Electrical isolation of devices on an integrated circuit (IC), such as, transistors disposed on a semiconductor substrate, is critical to the proper functioning of the IC. Current leakage from one device to another, i.e. across the isolation region between the devices, is a persistent problem as ICs become increasingly smaller. Current leakage may occur, e.g., between the drain of one transistor and the source of another in N-channel metal oxide semiconductors (NMOS) or P-channel metal oxide semiconductors (PMOS), or between two sources or two drains in complementary metal oxide semiconductors (CMOS). Problems resulting from current leakage include affecting the state (ON or OFF) of a transistor, causing undesirable DC power dissipation, noise-margin degradation and voltage shift on dynamic nodes. Also, current leakage in the isolation region can escalate latchup, a form of isolation breakdown between the power and ground rails in CMOS and bipolar CMOS (BiCMOS) ICs, typically resulting in permanent circuit failure.
Various isolation technologies have been developed, dating back to the 1960s. One method is Local Oxidation of Silicon (LOCOS) isolation. LOCOS includes growing an oxide barrier from an oxide layer applied beneath a nitride layer over silicon. LOCOS isolation, however, is inadequate for submicron MOSFETs because of the relatively large size of the LOCOS structure. Polybuffered LOCOS (PBL) and shallow-trench refill isolation (STI) are more commonly employed in higher-count devices. PBL includes depositing a polysilicon layer over the pad oxide layer, then applying the nitride layer. The addition of the polysilicon layer provides stress relief during oxide growth to reduce undesirable effects such as "bird's beak."
Conventional STI processes typically include first etching a relatively shallow trench in the silicon substrate (i.e. 0.3-0.5 microns deep) between two devices, and then refilling the trench with an insulative material. The insulative material is selectively etched so that the insulative material remains in the trench. The insulative material serves to limit the flow of current between the doped regions of adjacent devices on the substrate and inhibits the formation of a parasitic transistor.
When the circuit size scales down even further to the ultra-large scale integrated (ULSI) circuit level, polybuffered LOCOS and conventional STI processes become inadequate. Conventional STI processes require a certain trench depth to achieve sufficient electrical isolation to prevent the above-stated problems. However, conventional plasma etching processes are limited in that the aspect ratio (width/depth) cannot be scaled down aggressively due to limitations in the etching chemistry. Typically, the aspect ratio cannot exceed 1:5 units of width:depth of the trench. Thus, if the ratio of width to depth of the isolation structure cannot be increased due to limitations of conventional etching processes, and the depth of the trench must be at least 0.3 microns deep to adequately reduce leakage, then the width of the trench cannot be reduced under conventional processes to any narrower than about 0.06 microns. Consequently, the packing density of the IC is severely limited by conventional STI processes.
Thus, there is a need for an IC having isolation structures and an improved method of making such an integrated circuit that has very shallow trench isolation structures to facilitate increased packing density of devices on the IC while still maintaining adequate electrical isolation between the devices. Further, there is a need to increase the isolation ability of trench isolation structures without increasing the width of the structures.